Timing behavior of integrated circuits traditionally have been dictated by transistor considerations, mostly transistor travel time and the number of logic levels a signal traverses during a clock cycle. Accurate models of transistor device parameters were the key element for the prediction of circuit timing behavior. Wire delay, conversely, was at most 20% of the total delay in the circuit. Consequently, high-precision measurements of wire delay were superfluous.
More recently, with the advent of deep submicron integrated circuits, wire delays have become a major contributor to the total signal delay. For example, up to 75% of the total delay (in the absence of repeaters) can be accounted by wire delay. The are several reasons for this increased importance in wire delays: (1) transistor contribution to wire delay decreases with scaling (i.e., the semi-uniform decrease of transistor, and wire dimensions) and, (2) the capacitance of wires varies slowly with scaling.
The combination of (1) and (2) makes the relative contribution of wire capacitance to the total delay increasingly important with technology scaling. This new technological regime (that emerged when minimal dimensions reached 0.25 microns) increases the need for accuracy in the determination of capacitance. The proper determination of wire delay also requires the knowledge of total capacitance and cross-coupling capacitance to nearest neighbors. The presence of cross-coupling capacitance can impact the delay estimation by nearly 400% in the presence of switching activity by nearby wires.
Another physical effect that impacts the proper behavior of integrated circuits is that due to noise on quite lines. The controllability of the noise on nearby quite lines demands the accurate knowledge of different cross-coupling capacitance terms. It is therefore desirable to come up with a methodology that can determine with high precision and accuracy each one of the cross-coupling capacitance terms that contribute to the total capacitance of a wire.
One approach to accurate wire capacitance measurement is provided by B. W. McGaughy, J. C. Chen, D. Sylvester and C. Hu “A Simple Method for On-Chip Sub-Femto Farad Interconnect Capacitance Measurement,” IEEE Electron. Device Letters, Vol. 18, No. 1, pp. 21–23, January 1997, (hereinafter referred to as “the IEEE paper”).
FIG. 1 represents the circuit 10 used in the IEEE paper to measure cross-coupling capacitance between the two wires 30, 32 on the right hand side of the figure. The circuit 10 has a mirror structure formed by two inverter-like configurations 14, 16 for implementing a comparative method of measuring capacitance. The configuration 14 includes a PMOS transistor 18 connected in series to an NMOS transistor 20 with the wire 12 connected therebetween. Gates of the transistors 18, 20 are coupled to input signals V1, V2 for controlling the charging and discharging of the wire 12. An ammeter 22 is also coupled in series with transistors 18, 20 to measure the current needed to charge the wire 12. The second inverter-like configuration 16 is intended to be an exact replication of the first configuration 14. For example, the second configuration 16 includes a PMOS transistor 24 coupled in series with an NMOS transistor 26 and an ammeter 28. A second wire 30 is coupled between the transistors 24, 26 and is charged and discharged by input signals V1 and V2, similar to wire 12. A third wire 32 is placed near wire 30 so that a capacitive coupling occurs between wires 30, 32, wire 32 being grounded.
FIG. 2 shows voltage waveforms used in the circuit of FIG. 1. The voltage waveforms are non-overlapping to ensure no current path exists (except for leakage) between Vdd and ground. Using these waveforms, the charge, Q, on the wire 12 can be measured using the formula Q=(Csubstrate+Cother) Vdd, where Csubstrate is the capacitance between the wire 12 and the substrate of the integrated circuit and Cother includes other capacitances associated with the configuration 14, including the capacitance of the transistor 18.
Similarly, the charge on wire 30 can be calculated as Q′=(Csubstrate+Cother+Ccross-coupling) Vdd, where Csubstrate is the capacitance between the wire 30 and the substrate of the integrated circuit and Cother includes other capacitance associated with the configuration 16, including the capacitance associated with the transistor 24. Ccross-coupling is the cross-coupling capacitance between the wires 30, 32.
By subtracting Q from Q′, theoretically, only the Ccross-coupling remains. However, this determination of the cross-coupling capacitance assumes that the electric field configuration between wire 14 and substrate on the left side of FIG. 1 is identical to the electric field configuration between wire 30 and substrate on the right side. In reality, these two configurations are not identical. In particular, the wire 32 affects the field distribution causing a charge redistribution error in Csubstrate of wire 30. This change in Csubstrate can be significant causing errors in the measurement of the cross-coupling capacitance. Additionally, the transistors 18, 20 are not identical to transistors 24, 26, which introduces additional errors.
FIG. 3 shows a configuration where the measurement of the cross-coupling capacitance using the method described in the IEEE paper can result in a 70% error. In this example, the wires 36, 38 are on the same metal layer as wire 40 and separated by minimum distance and, under these condition, the charge redistribution effect to the substrate is much larger.
The error of the IEEE method, on the other hand, can be made quite small for total capacitance measurements only, with a simple change to the structure in FIG. 1, consisting of eliminating wire 12 on the left hand side of FIG. 1. Transistor inequality errors persist in total capacitance measurements.
Therefore, there is a need for a more effective technique to measure the cross-coupling capacitance in integrated circuits.